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1 SED157A series overview the SED157A series is a single-chip dot matrix liquid crystal display driver that can be connected directly to a microprocessor bus. eight-bit parallel or serial display data transmitted from the microprocessor is stored in the internal display data ram, and the chip generates liquid crystal drive signals, independently of the micropro- cessor. it has a on-chip 65 256-bit display data ram, and there is a one-to-one correspondence between the dot pixel on the liquid crystal panel pixels and internal ram bit. this feature ensures implementation of highly free display. the SED157A series incorporate 65 common output circuits and 224 segment output circuits. a single chip can drive a 65 224 dot display (capable of displaying 14 columns 4 rows with 16 16-dot kanji font). further, display capacity can be extended by designing two chips in a master/display configuration. the SED157A series can read and write ram data with the minimum current consumption because it does not require any external operation clock. also it incorporates a lcd power supply featuring a very low current consumption, a lcd drive power voltage regulator resistor and a display clock cr oscillator circuit. this allows the display system of a high-performance for handy equipment to be realized at the minimum power consump- tion and minimum component configuration. features direct display of ram data using the display data ram ram bit data ? ...... goes on. ? ...... goes off (at display normal rotation). ram capacity 65 256 = 16,640 bits liquid crystal drive circuit 65 circuits for the common output and 224 circuits for the segment output high-speed 8-bit mpu interface (both the 80 and 68 series mups can directly be connected.)/serial inter- face enabled abundant command functions display data read/write, display on/off, display normal rotation/reversal, page address set, display start line set, column address set, status read, power supply save display all lighting on/off, lcd bias set, read modify write, segment driver direction select, electronic control, v5 voltage adjusting built-in resistance ratio set, static indicator, n line alternating current reversal drive, common output state selection, and built-in oscillator circuit on built-in static drive circuit for indicators (one set, blinking speed variable) SED157A series dot matrix lcd driver pf1102-01 support up to 65 224 display built-in power supply circuit for lcd
2 SED157A series series specification product name duty bias seg dr com dr v reg temperature shipping form gradient SED157Ad 0b 1/65 1/9, 1/7 224 65 ?.05%/ c bare chip SED157At 0* 1/65 1/9, 1/7 224 65 ?.05%/ c tcp built-in power supply circuit for low power supply liquid crystal drive booster circuit (boosting magnification - double, triple, quadruple, boosting reference power supply external input enabled) 3% high accuracy alternating current voltage adjusting circuit (temperature gradient: ?.05%/ c) built-in v 5 voltage adjusting resistor, built-in v 1 to v 4 voltage generation split resistors, built-in electronic control function, and voltage follower built-in cr oscillator circuit (external clock input enabled) ultra-low power consumption power supplies logic power supply: v dd ?v ss = 1.8 to 5.5 v boosting reference power supply: v dd ?v ss = 1.8 to 6.0 v liquid crystal drive power supply: v 5 ?v dd = ?.5 to ?8.0 v wide operating temperature range ?0 to 85 c cmos process shipping form bare chip, tcp no light-resistant and radiation-resistant design are provided.
3 SED157A series block diagram v ss v dd v 1 v 2 v 3 v 4 v 5 v out v ss2 v r v rs irs hpm cap1+ cap1 cap2 cap2+ cap3 frs cls oscillator circuit display timing generator circuit line address i/o buffer fr cl sync dof m/s cs1 cs2 a0 rd (e) wr (r/w) p/s res d7 (si) d6 (scl) d5 d4 d3 d2 d1 d0 seg0 seg223 com0 com63 coms coms com drivers seg drivers display data latch circuit display data ram 256 x 65 column address status command decoder interface bus holder shift register power supply circuit page address mpu
4 SED157A series pin assignment chip specification SED157A series (0, 0) y x 118 117 1 153 382 152 417 383 die no. d157ad 0b item size unit xy chip size 16.65 2.90 mm chip thickness 0.625 mm bump pitch 69 (min.) m bump size pad no.1 to 117 85 85 m pad no.118 85 73 m pad no.119 to 151 85 47 m pad no.152 85 73 m pad no.153 73 85 m pad no.154 to 381 47 85 m pad no.382 73 85 m pad no.383 86 73 m pad no.384 to 416 85 47 m pad no.417 85 73 m bump height 17 (typ.) m
5 SED157A series pin description power supply pin lcd power supply circuit pin pin name i/o description number of pins cap1+ o boosting capacitor positive side connecting pin. connects a capacitor between 2 the pin and cap1 pin. cap1 o boosting capacitor negative side connecting pin. connects a capacitor between 2 the pin and cap1+ pin. cap2+ o boosting capacitor positive side connecting pin. connects a capacitor 2 between the pin and cap2 pin. cap2 o boosting capacitor negative side connecting pin. connects a capacitor between 2 the pin and cap2+ pin. cap3 o boosting capacitor negative side connecting pin. connects a capacitor between 2 the pin and cap1+ pin. v out o boosting output pin. connects a capacitor between the pin and v ss2 .2 v r i voltage adjusting pin. applies voltage between v dd and v 5 using a split resistor. 1 valid only when the v 5 voltage adjusting built-in resistor is not used (irs= l ) do not use vr when the v 5 voltage adjusting built-in resistor is used (irs= h ) pin name i/o description number of pins v dd power commonly used with the mpu power supply pin v cc .12 supply v ss power 0 v pin connected to the system ground (gnd) 9 supply v ss2 power boosting circuit reference power supply for liquid crystal drive 5 supply v rs power external input pin for liquid crystal power supply voltage supply adjusting circuit 2 they are set to open v 1 , v 2 power multi-level power supply for liquid crystal drive. the voltage specified according 10 v 3 , v 4 supply to liquid crystal cells is impedance-converted by a split resistor or operation v 5 amplifier (op amp) and applied. the potential needs to be specified based on v dd to establish the relationship of dimensions shown below: v dd (=v 0 ) v 1 v 2 v 3 v 4 v 5 master operation when the power supply is on, the following voltages are applied to v 1 ~ v 4 from the built-in power supply circuit. the selection of the voltages is determined using the lcd bias set command. v 1 1/9 v 5 1/7 v 5 v 2 2/9 v 5 2/7 v 5 v 3 7/9 v 5 5/7 v 5 v 4 8/9 v 5 6/7 v 5
6 SED157A series system bus connecting pins pin name i/o description number of pins d7 to d0 i/o an 8-bit bidirectional data bus is used to connect an 8-bit or 16-bit standard 8 (si) mpu data bus. (scl) when the serial interface is selected (p/s= l ), d7: serial data entry pin (si) d6: serial clock input pin (scl) in this case, d0 to d5 are set to high impedance. when chip select is in the non-active state, d0 to d7 are set to high impedance. a0 i normally the lowest order bit of the mpu address bus is connected to 1 discriminate data / commands. a0= h : indicates that d0 to d7 are display data. a0= l : indicates that d0 to d7 are control data. res i initialized by setting res to l .1 reset operation is performed at the res signal level. cs1 i chip select signal. when cs1= l and cs2= h , this signal becomes active 2 cs2 and the input/output of data/commands is enabled. rd i when the 80 series mpu is connected, active l is set. 1 (e) pin that connects the rd signal of the 80 series mpu. when this signal is l , the SED157A series data bus is set in the output state. when the 68 series mpu is connected, active h is set. 68 series mpu enable clock input pin wr i when the 80 series mpu is connected, active l is set. 1 (r/w) pin that connects the wr signal of the 80 series mpu. the data bus signal is latched on the leading edge of the wr signal. when the 68 series mpu is connected, read/write control signal input pin r/w= h : read operation r/w= l : write operation frs o output pin for static drive 1 used together with the sync pin c86 i mpu interface switching pin 1 c86= h : 68 series mpu interface c86= l : 80 series mpu interface p/s i switching pin for parallel data entry/serial data entry 1 p/s= h : parallel data entry p/s= l : serial data entry according to the p/s state, the following table is given. when p/s= l , d0 to d5 are set to high impedance. d0 to d5 can be h , l , or open . rd(e) and wr (r/w) are fixed to h or l . for the serial data entry, ram display data cannot be read. p/s data/ data read/write serial clock command h a0 d0 to d7 rd, wr l a0 si (d7) write-only scl (d6)
7 SED157A series pin name i/o description number of pins cls i pin that selects the validity/invalidity of the built-in oscillator circuit 1 for display clocks. cls= h : built-in oscillator circuit valid cls= l : built-in oscillator circuit invalid (external input) when cls= l , display clocks are input from the cl pin. when the SED157A series is used for the master/slave configuration, each of the cls pins is set to the same level together. m/s i pin that selects the master/slave operation for the SED157A series. 1 the liquid crystal display system is synchronized by outputting the timing signal required for the liquid crystal display for the master operation and inputting the timing signal required for the liquid crystal display for the slave operation. m/s= h : master operation m/s= l : slave operation according to the m/s and cls states, the following table is given. cl i/o display clock i/o pin 1 according to the m/s and cls states, the following table is given. when the SED157A series is used for the master/slave configuration, each cl pin is connected. fr i/o liquid crystal alternating current signal i/o pin 1 m/s= h : output m/s= l : input when the SED157A series is used for the master/slave configuration, each fr pin is connected. sync i/o liquid crystal synchronizing current signal i/o pin 2 m/s= h : output m/s= l : input when the SED157A series is used for the master/slave configuration, each sync pin is connected. dof i/o liquid crystal display blanking control pin 1 m/s= h : output m/s= l : input when the SED157A series is used for the master/slave configuration, each dof pin is connected. irs i v 5 voltage adjusting resistor selection pin 1 irs= h : built-in resistor used irs= l : built-in resistor not used. the v 5 voltage is adjusted by the v r pin and stand-alone split resistor. valid only at master operation. the pin is fixed to h or l at slave operation. hpm i power supply control pin of the power supply circuit for liquid 1 crystal drive hpm= h : normal mode hpm= l : high power supply mode valid only at master operation. the pin is fixed to h or l at slave operation. m/s cls cl h h output l input l h input l input display clock master slave built-in oscillator circuit used h h external input l l m/s cls oscillator power supply cl fr sync frs dof circuit circuit h h valid valid output output output output output l invalid valid input output output output output l h invalid invalid input input input output input l invalid invalid input input input output input
8 SED157A series test pin pin name i/o description number of pins test1 to i/o ic chip test pin. fix the pin to h .8 4, 10 to 13 test5 to i/o ic chip test pin. take into consideration so that the capacity of lines cannot be 13 9, 14 to 16 exhausted by setting the pin to open. liquid crystal drive pin pin name i/o description number of pins seg0 o output pins for the lcd segment drive. contents of the display ram and fr 224 to signal are combined to select a desired level among v dd , v 2 , v 3 and v 5 . seg223 com0 output pins for the lcd common drive. scan data and fr signal are combined 64 to to select a desired level among v dd , v 1 , v 4 and v 5 . com63 coms o indicator dedicated com output pin 2 set to open when not used when coms is used for the master/slave configuration, the same signal is output to both the master and slave. output voltage ram data fr display display reversal normal operation hh v dd v 2 hl v 5 v 3 lh v 2 v dd ll v 3 v 5 power save v dd scanning data fr output voltage hhv 5 hlv dd lhv 1 llv 4 power save v dd
9 SED157A series notes: 1.the values of the v ss2 , v 1 to v 5 , and v out voltages are based on v dd =0 v. 2.the v 1 , v 2 , v 3 , and v 4 voltages must always satisfy the condition of v dd v 1 v 2 v 3 v 4 v 5 . 3.insure that voltage levels v ss2 and v out are always such that the relationship of v dd v ss v ss2 v out is maintained. 4.when lsi is used exceeding the absolute maximum ratings, the lsi may be damaged permanently. besides, it is desirable that the lsi should be used in the electrical characteristics condition for normal operation. if this condition is exceeded, the lsi may malfunction and have an adverse effect on the reliability of the lsi. v dd v dd v ss2 , v 1 ~ v 4 v 5 , v out v cc gnd v ss SED157A side system (mpu) side absolute maximum ratings v ss =0 v unless specified otherwise item symbol specification value unit power supply voltage v dd 0.3 to +7.0 v power supply voltage (2) 7.0 to +0.3 (based on v dd ) at triple boosting v ss2 6.0 to +0.3 at quadruple boosting 4.5 to +0.3 power supply voltage (3) (based on v dd )v 5 , v out 22.0 to +0.3 power supply voltage (4) (based on v dd )v 1 , v 2 , v 3 , v 4 v 5 to +0.3 input voltage v in 0.3 to v dd +0.3 output voltage v out 0.3 to v dd +0.3 operating temperature t opr 40 to +85 c storage temperature tcp t str 55 to +100 bare chip 55 to +125
10 SED157A series dc characteristics v ss =0 v, v dd =3.0 v 10%, and ta= 40 to 85 c specification value applicable item symbol condition min. typ. max. unit pin operating recommended v dd 2.7 3.3 v v dd voltage operation (1) operable v dd 1.8 5.5 v dd operating recommended v ss2 (based on v dd ) 3.3 2.7 v ss2 voltage operation (2) operable v ss2 (based on v dd ) 6.0 1.8 v ss2 operating operable v 5 (based on v dd ) 18.0 4.5 v 5 voltage operable v 1 , v 2 (based on v dd ) 0.4 v 5 v dd v 1 , v 2 (3) operable v 3 , v 4 (based on v dd )v 5 0.6 v 5 v 3 , v 4 high level input voltage v ihc 0.8 v dd v dd low level input voltage v ilc v ss 0.2 v dd high level output voltage v ohc i oh = 0.5ma 0.8 v dd v dd low level output voltage v olc i ol =0.5ma v ss 0.2 v dd input leak current i li v in =v dd or v ss 1.0 1.0 a output leak current i lo 3.0 3.0 liquid crystal driver r on ta=25 cv 5 = 14.0v 2.0 3.5 k ? segn on resistance (based on v dd )v 5 = 8.0v 3.2 5.4 comn static current consumption i ssq 0.01 5 av ss , v ss2 output leak current i 5q v 5 = 18.0v (based on v dd ) 0.01 15 v 5 input pin capacity c i ta=25 c, f=1mhz 5.0 8.0 pf oscillating built-in f osc ta=25 c 18 22 26 khz frequency oscillation external input f cl 4.5 5.5 6.5 cl specification value applicable item symbol condition min. typ. max. unit pin input voltage v ss2 at triple boosting 6.0 1.8 v v ss2 (based on v dd ) v ss2 at quadruple boosting 5.0 1.8 v ss2 (based on v dd ) boosting output voltage v out (based on v dd ) 20.0 v out voltage adjusting circuit v out (based on v dd ) 20.0 6.0 v out operating voltage v/f circuit operating v 5 (based on v dd ) 18.0 4.5 v 5 voltage reference voltage v reg0 ta=25 c, 0.05%/ c 2.04 2.10 2.16 built-in power supply circuit
11 SED157A series dynamic current consumption value (1) during display operation and built-in power supply off current values dissipated by the whole ic when the external power supply is used display all white ta=25 c specification value item symbol condition min. typ. max. unit remarks dynamic current i dd v dd =5.0v, v 5 v dd = 11.0v 25 42 a consumption (1) v dd =3.0v, v 5 v dd = 11.0v 25 42 dynamic current consumption value (2) during display operation and built-in power supply on current values dissipated by the whole ic containing the built-in power supply circuit display checker pattern ta=25 c specification value item symbo condition min. typ. max. unit remarks dynamic current i dd v dd =5.0v, normal mode 92 154 a consumption (2) triple boosting v 5 v dd = 11.0v high power mode 242 405 v dd =3.0v, normal mode 129 216 quadruple boosting v 5 v dd = 11.0v high power mode 310 518 display checker pattern ta=25 c specification value item symbo condition min. typ. max. unit remarks dynamic current i dd v dd =5.0v, v 5 v dd = 11.0v 38 64 a consumption (1) v dd =3.0v, v 5 v dd = 11.0v 38 64 display checker pattern ta=25 c specification value item symbo condition min. typ. max. unit remarks dynamic current i dd v dd =5.0v, normal mode 132 221 a consumption (2) triple boosting v 5 v dd = 11.0v high power mode 280 468 v dd =3.0v, normal mode 167 279 quadruple boosting v 5 v dd = 11.0v high power mode 350 585 current consumption at power save v ss =0v and v dd = 3.0 v 10% ta=25 c specification value item symbol condition min. typ. max. unit remarks sleep state i dds1 0.01 5 a stand-by state i dds2 48
12 SED157A series timing characteristics system bus read/write characteristics 1 (80 series mpu) a0 cs1 (cs2="1") wr, rd d0 to d7 (write) d0 to d7 (read) t acc8 t oh8 t ds8 t cyc8 t ah8 t aw8 t cclr , t cclw t cchr , t cchw t dh8 cs1 (cs2="1") wr, rd *1 *2 [v dd =4.5v to 5.5v, ta= 40 to 85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah8 0 ns address setup time t aw8 0 system cycle time a0 t cyc8 333 control l pulse width (wr) wr t cclw 30 control l pulse width (rd) rd t cclr 70 control h pulse width (wr) wr t cchw 30 control h pulse width (rd) rd t cchr 30 data setup time d0 to d7 t ds8 30 data hold time t dh8 10 rd access time t acc8 c l =100pf 70 output disable time t oh8 550
13 SED157A series [v dd =1.8v to 2.7v, ta= 40 to 85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah8 0 ns address setup time t aw8 0 system cycle time a0 t cyc8 1000 control l pulse width (wr) wr t cclw 120 control l pulse width (rd) rd t cclr 240 control h pulse width (wr) wr t cchw 120 control h pulse width (rd) rd t cchr 120 data setup time d0 to d7 t ds8 80 data hold time t dh8 30 rd access time t acc8 c l =100pf 280 output disable time t oh8 10 200 notes: 1.this is the case of accessing by wr and rd when cs1 = l . 2.this is the case of accessing by cs1 when wr and rd = l . 3.the rise and fall times (t r and t f ) of the input signal are specified for less than 15 ns. when using the system cycle time at high speed, they are specified for (t r +t f ) (t cyc8 t cclw t cchw ) or (t r +t f ) (t cyc8 t cclr t cchr ). 4.all timings are specified based on the 20 and 80% of v dd . 5.t cclw and t cclr are specified for the overlap period when cs1 is at l (cs2= h ) level and wr, rd are at the l level. [v dd =2.7v to 4.5v, ta= 40 to 85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah8 0 ns address setup time t aw8 0 system cycle time a0 t cyc8 500 control l pulse width (wr) wr t cclw 60 control l pulse width (rd) rd t cclr 120 control h pulse width (wr) wr t cchw 60 control h pulse width (rd) rd t cchr 60 data setup time d0 to d7 t ds8 40 data hold time t dh8 15 rd access time t acc8 c l =100pf 140 output disable time t oh8 10 100
14 SED157A series system bus read/write characteristics 2 (68 series mpu) [v dd =4.5v to 5.5v, ta= 40 to 85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah6 0 ns address setup time t aw6 0 system cycle time t cyc6 333 data setup time d0 to d7 t ds6 30 data hold time t dh6 10 access time t acc6 cl=100pf 70 output disable time t oh6 10 50 enable h pulse width read e t ewhr 70 write t ewhw 30 enable l pulse width read e t ewlr 30 write t ewlw 30 a0 r/w cs1 (cs2="1") e d0 to d7 (write) d0 to d7 (read) t acc6 t oh6 t ds6 t cyc6 t ah6 t aw6 t ewhr , t ewhw t ewlr , t ewlw t dh6 cs1 (cs2="1") e *1 *2
15 SED157A series [v dd =2.7v to 4.5v, ta= 40 to 85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah6 0 ns address setup time t aw6 0 system cycle time t cyc6 500 data setup time d0 to d7 t ds6 40 data hold time t dh6 15 access time t acc6 cl=100pf 140 output disable time t oh6 10 100 enable h pulse width read e t ewhr 120 write t ewhw 60 enable l pulse width read e t ewlr 60 write t ewlw 60 [v dd =1.8v to 2.7v, ta= 40 to 85 c] specification value item signal symbol condition min. max. unit address hold time a0 t ah6 0 ns address setup time t aw6 0 system cycle time t cyc6 1000 data setup time d0 to d7 t ds6 80 data hold time t dh6 30 access time t acc6 c l =100pf 280 output disable time t oh6 10 200 enable h pulse width read e t ewhr 240 write t ewhw 120 enable l pulse width read e t ewlr 120 write t ewlw 120 notes: 1.this is the case of accessing by e when cs1 = l . 2.this is the case of accessing by cs1 when e = h . 3.the rise and fall times (t r and t f ) of the input signal are specified for less than 15 ns. when using the system cycle time at high speed, they are specified for (t r +t f ) (t cyc6 t ewlw t ewhw ) or (t r +t f ) (t cyc6 t ewlr t ewhr ). 4.all timings are specified based on the 20 and 80% of v dd . 5.t ewlw and t ewlr are specified for the overlap period when cs1 is at l (cs2 = h ) level and e is at the h level.
16 SED157A series serial interface t css t csh t sah t shw t sdh t sds t slw t f t r t scyc t sas cs1 (cs2="1") a0 scl si [v dd =4.5v to 5.5v, ta= 40 to 85 c] specification value item signal symbol condition min. max. unit serial clock cycle scl t scyc 200 ns scl h pulse width t shw 75 scl l pulse width t slw 75 address setup time a0 t sas 50 address hold time t sah 100 data setup time si t sds 50 data hold time t sdh 50 cs-scl time cs t css 100 t csh 100 [v dd =2.7v to 4.5v, ta= 40 to 85 c] specification value item signal symbol condition min. max. unit serial clock cycle scl t scyc 250 ns scl h pulse width t shw 100 scl l pulse width t slw 100 address setup time a0 t sas 150 address hold time t sah 150 data setup time si t sds 100 data hold time t sdh 100 cs-scl time cs t css 150 t csh 150
17 SED157A series display control output timing t dfr cl (out) fr t dsnc sync [v dd =4.5v to 5.5v, ta= 40 to 85 c] specification value item signal symbol condition min. typ. max. unit fr delay time fr t dfr c l =50pf 10 40 ns sync delay time sync t dsnc c l =50pf 10 40 ns [v dd =2.7v to 4.5v, ta= 40 to 85 c] specification value item signal symbol condition min. typ. max. unit fr delay time fr t dfr c l =50pf 20 80 ns sync delay time sync t dsnc c l =50pf 20 80 ns [v dd =1.8v to 2.7v, ta= 40 to 85 c] specification value item signal symbol condition min. typ. max. unit fr delay time fr t dfr c l =50pf 50 200 ns sync delay time sync t dsnc c l =50pf 50 200 ns notes: 1.valid only when the master mode is selected. 2.all timings are specified based on the 20 and 80% of v dd . 3.pay attention not to cause delays of the timing signals c l , fr and sync to the salve side by wiring resistance, etc., while master/slave operations are in progress. if these delays occur, indication failures such as flickering may occur. [v dd =1.8v to 2.7v, ta= 40 to 85 c] specification value item signal symbol condition min. max. unit serial clock cycle scl t scyc 400 ns scl h pulse width t shw 150 scl l pulse width t slw 150 address setup time a0 t sas 250 address hold time t sah 250 data setup time si t sds 150 data hold time t sdh 150 cs-scl time cs t css 250 t csh 250 notes: 1.the rise and fall times (t r and t f ) of the input signal are specified for less than 15 ns. 2.all timings are specified based on the 20 and 80% of v dd .
18 SED157A series reset input timing t rw t r completion of reset resetting res internal state [v dd =4.5v to 5.5v, ta= 40 to 85 c] specification value item signal symbol condition min. typ. max. unit reset time t r 0.5 s reset l pulse width res t rw 0.5 [v dd =2.7v to 4.5v, ta= 40 to 85 c] specification value item signal symbol condition min. typ. max. unit reset time t r 1 s reset l pulse width res t rw 1 [v dd =1.8v to 2.7v, ta= 40 to 85 c] specification value item signal symbol condition min. typ. max. unit reset time t r 1.5 s reset l pulse width res t rw 1.5 note: all timings are specified based on the 20 and 80% of v dd . electronic devices marketing division notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arisi ng out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no re presentation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material wil l be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject rela ting to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 2000 all right reserved. all other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. first issue february, 2000 printed in japan h ic marketing & engineering group ed international marketing department i (europe, u.s.a) 421-8 hino, hino-shi, tokyo 191-8501, japan phone: 042 587 5812 fax: 042 587 5564 ed international marketing department ii (asia) 421-8 hino, hino-shi, tokyo 191-8501, japan phone: 042 587 5814 fax: 042 587 5110 http://www.epson.co.jp/device/ electronic devices information on the epson www server.

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